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GPU Fleet Reliability & Observability / 22
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A GPU computes the wrong answer and reports no error. How would you detect that, and what does it look like in a training run?

Error correction catches memory faults and reports them. Nothing catches an arithmetic unit that occasionally returns a wrong product, which is why this class is found by comparing results rather than by reading counters. Three detection strategies with their costs, and the signature in a loss curve.

Updated Sep 2026 · Grounded in real AI infrastructure interview loops and written to a senior-engineer editorial bar, with every number worked and every diagram hand-built.

Error correction catches memory faults and reports them. Nothing catches an arithmetic unit that occasionally returns a wrong product, which is why this class is found by comparing results rather than by reading counters. Three detection strategies with their costs, and the signature in a loss curve.

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The concepts behind this question

Ranked by how closely each one overlaps this question's topic, so the first card is the thing to read if the answer above moved too fast.

Foundational
🖧 Hardware & Cluster Build-Out
Rack Power Delivery and BuswaysA GPU rack has gone from 10 kW to over 120 kW in a few generations, and the electrical design changed with it. At 132 kW on a 415 V three-phase feed a rack draws about 184 amps, which is past what a normal power strip carries, so distribution moves to overhead busway and the rack takes redundant high-current taps. On top of the steady draw sits a synchronized transient every training step, because thousands of GPUs finish a collective at the same instant, and that swing is what sizes the upstream equipment.
Foundational
🩺 Fleet Reliability & Observability
GPU Failure Modes and XID ErrorsWhen a GPU misbehaves, the NVIDIA driver writes an XID line to the kernel log, and the number on that line is the first and often the only clue to what happened. Fleet engineers learn a dozen of them the way doctors learn a dozen lab values: 13 and 31 are almost always the application, 48 and 95 are memory that needs a reset, 63 and 64 are the row remapper reporting or failing, 74 is the NVLink fabric, 79 is a GPU that has vanished from the PCIe bus. This page gives the taxonomy, the decision for each (retry, reset, drain, RMA), and the derivation of how often a big fleet should expect each.
Core
🩺 Fleet Reliability & ObservabilitySign in
DCGM and GPU TelemetryNVIDIA's Data Center GPU Manager reads a GPU's counters, runs its diagnostics and exports both to the monitoring stack, and nearly every fleet's dashboards and alerts are built on it. The skill is knowing which of its hundreds of fields carry signal: the profiling metrics that say whether the tensor cores are busy (not the utilization number everyone reads first), the error counters that predict a failure, the throttle reasons that explain a slow step, and the diagnostic levels that decide whether a node returns to the pool. This page walks those fields, derives an MFU estimate from them, and gives a fleet's alert thresholds.
Advanced
🩺 Fleet Reliability & Observability🔒 Premium
ECC, Row Remapping and Memory ErrorsHBM stacks flip bits, and the difference between a fleet that shrugs and one that loses a training step to corruption is error-correcting codes plus the machinery that retires bad memory before it produces a double-bit error. A single-bit error is corrected silently and counted; a double-bit error is detected, kills the process, and on Ampere and later triggers the row remapper to swap the failing row for a spare at the next reset. This page explains the codes, the remapper's states, how to read the counters as a prediction of failure, and the RMA rules a fleet applies.
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FEDITOR'S NOTE

Scored on knowing this class evades ECC because it is computational rather than storage, on the three detection strategies with their overheads, and on the loss-curve signature and how it differs from a normal divergence.

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