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TPU Architecture and Systolic Arrays

A TPU is a matrix unit first and a processor second: a systolic array that streams activations through a grid of multiply-accumulate cells holding stationary weights, fed by a compiler rather than a warp scheduler, and scaled out over a dedicated inter-chip interconnect into pods of thousands. The roofline thinking transfers from GPUs unchanged; the workflow does not, which is what the Google loop tests.

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Tensor Cores and Matrix Units Roofline Model GPU Generations: A100 to Blackwell Cerebras, Groq and Dataflow Accelerators Collective Communication Primitives Topology-Aware Communication

PRACTICE THIS IN REAL QUESTIONS

GPU & Accelerator ArchitectureYou have trained on GPUs. What transfers to training on TPUs, and what do you have to relearn?→GPU & Accelerator ArchitectureExplain how a systolic array computes a matrix multiply. Why is it efficient, and why does it want big square tiles?→Distributed Training & ParallelismHow is training on TPUs with JAX different from training on GPUs with PyTorch? What do you stop doing by hand?→Open-Weights Models & Serving EnginesYou must serve a frontier open-weights model on non-NVIDIA accelerators. Plan it.→GPU & Accelerator ArchitectureWalk me through the CUDA execution model: what are grids, blocks and warps, and what does the hardware actually schedule?→GPU & Accelerator ArchitectureDescribe the GPU memory hierarchy. Where can a byte live on an H100, and what does each level cost?→